1. Field of the Invention
The present invention relates to the field of emulation systems. More specifically, the present invention relates to methods and apparatus for tracing any node in an emulator.
2. Background Information
Emulation systems for emulating circuit designs are known in the art. Typically, prior art emulation systems are formed using conventional general purpose field programmable gate arrays (FPGAs). A circuit design to be emulated is "realized" on the emulation system by compiling a "formal" description of the circuit design, and mapping the circuit design onto the logic elements (LEs) of the FPGAs.
Emulation systems for emulating circuit designs are particularly valuable because they allow complex circuits to be emulated in both a cost-effective and time-effective manner. Such emulation systems are also valuable because they allow signals to be output from the FPGAs for testing and debugging the circuit designs, thereby providing for "tracing" of signals.
However, these conventional emulation systems have several disadvantages. These disadvantages include the limitation that the states of signals at nodes within the LEs are not observable. For example, combinatorial logic mapped onto an LE may include several nodes which do not have signals that are output by the LE and thus are not observable. These nodes are referred to as "hidden" nodes. These hidden nodes can be made unhidden by mapping one circuit element to each LE, however, such inefficient mapping would be extremely wasteful of the precious LE resources.
Thus, it is desirable to have an emulation system and methodology for operating therein for tracing any node in an emulation, including hidden nodes. As will be described in more detail below, the present invention provides for such an emulation system that achieves these and other desired results, which will be apparent to those skilled in the art from the description to follow.